1. Field
Metrology and circuitry.
2. Description of Related Art
Microelectronic packaging technology, including methods to mechanically and electrically attach a silicon die (e.g., a microprocessor) to a substrate or other carrier continues to be refined and improved. Bumpless build-up layer (BBUL) packaging technology is one approach to a packaging architecture. Among its advantages, BBUL packaging technology eliminates the need for assembly, eliminates prior solder ball interconnections (e.g., flip-chip interconnections), reduces stress on interlayer dielectric of die due to die-to-substrate coefficient of thermal expansion (CTE) mismatch and reduces package inductance through elimination of core and flip-chip interconnect for improved input/output (I/O) and power delivery performance.
Typical of BBUL packaging technology is a die or dice embedded in a substrate such as a bismaleimide-triazine (BZT) laminate which has one or more build-up layers formed thereon. A process such as laser drilling and plating may be used for via formation to contacts on the die or dice. Build-up layers of, for example, alternating layers of dielectric (insulating) material and conductive material (e.g., traces or lines). Dielectric material is typically applied as a film and conductive material is applied and patterned by way of an electroless seeding process followed by electroplating of a conductor material such as copper.
Accurately measuring a thickness of an electrolessly introduced seed material such as copper is important for process control and minimization of yield losses during BBUL process development.